(Paper) Objective Questions for 8085 Microprocessor

Paper : Objective Questions for 8085 Microprocessor

1. In Synchronous data Transfer type both Transmitter and Receiver will operate in

a) Same Clock pulse

b) Different Clock pulse

c) None of the above



2. The term PSW Program Status word refers

a) Accumulator & Flag register

b) H and L register

c) Accumulator & Instruction register

d) B and C register



3. In 8085 the MAR, or ….. register, latches the address from the program counter. A bit later the MAR applies this address to the ……, where a read operations performed

a) Memory address, ROM

b) Memory address, RAM

c) Memory address, PROM

d) Memory address EPROM



4. In micro – processors like 8080 and the 8085, the …..cycle may have from one to live machine cycle

a) micro – instruction

b) source program

c) instruction

d) fetch cycle



5. Repeated addition is one way to do multiplication, programmed multiplication is used in most microprocessors because

a) that ALU’s can only add and subtract

b) this saves on memory

c) a separate set of instructions is needed for the two

d) None of the above.



6. A β€”β€” is used to isolate a bit, it does this because that ANI sets all other bits to Zero

a) subroutine

b) flag

c) label

d) mask



7. Interaction between a CPU and a peripheral device that takes place during and imput output operation is known as

a) handshaking

b) flagging

c) relocating

d) sub–routine



8. Addressing in which the instructions contains the address of the data to the operated on is known as

a) immediate addressing

b) implied addressing

c) register addressing

d) direct addressing



9. Resart is a special type of CALL in which

a) the address is programmed but not built into the hardware

b) the address is programmed built into the hardware

c) the address is not programmed but built into the hardware

d) None of the above



10. 8085 has …… software restarts and ….. hardware restarts

a) 10, 5

b) 8,4

c) 7,5

d) 6,6



11. Serial input data of 8085 can be loaded into bit 7 of the accumulator by

a) executing a RIM instruction

b) executing RST1

c) using TRAP

c) None of the above



12. The address to which a software or hardware restart branches is known as

a) vector location

b) SID

c) SOD

d) TRAP



13. TRAP is …..whereas RST 7.5, RST 6.5, RST 5.5 are….

a) maskable, non maskable

b) maskable, maskable

c) non - maskable, non – maskable

d) non - maskable, maskable



14. micro processor with a 16 – bit address bus is used in a linear memory selection configuration address bus lines are directly used as chip selects of memory chips with four memory chips. The maximum addressable memory space is

a) 64K

b) 16 K

c) 8K

d) 4K

15. How many outputs are there in the output of a 10-bit D/A converter?

a) 1000

b) 1023

c) 1024

d) 1224



16. The stack is a specialized temporary …… access memory during ….. and …… instructions

a) random, store, load

b) random, push, load

c) sequential, store, pop

d) sequential, push, pop



17. The memory address of the last location of a 1K byte memory chip is given as OFBFFH what will be the address of the first location ?

a) OF817H

b) OF818H

c) OF8OOH

d) OF801H



18. What is the direction of address bus ?

a) Uni – directional into microprocessors

b) Uni – directional out of microprocessors

c) Bi – directional

d) mixed direction is when lines into micro processor and some other out of micro

processes.



19. The No. of control lines are β€”β€”-



20. The length of A – register is β€”β€”- bits



21. The length of program counter is ——– bits



22. The length of stack pointer is ——– bits



23. The length of status word is β€”β€”- bits



24. The length of temporary register β€”β€”- bits



25. The length of Data buffer register β€”β€”- bits



26. The No. of flags are β€”β€”-



27. The No. of interrupts are β€”β€”-



28. The memory word addressing capability is β€”β€” K



29. The No. of input output ports can be accessed by direct method β€”β€”-



30. The No. of input output ports can be accessed by memory mapped method β€”β€” K



31. If instruction RST is written in a program the program will jump β€”β€”- location.



32. When TRAP interrupt is triggered program control is transferred to β€”β€”- location.



33. The RST 5.5 interrupt service routine start from ——– location.



34. What is the purpose of using ALE signal high ?

a) To latch low order address from bus to separate A0 – A7

b) To latch data Do – D 7 from bus go separate data bus

c) To disable data bus latch



35. What is the purpose of READY signal?

a) It is used to indicate to user that microprocessor is working and ready to use

b) It is used to provide for proper WAIT states when microprocessor is communicating with slow peripheral device.

c) It is used to provide for proper showing down of fast peripheral devices so as to communicate at micro processors speed.



36. What is the addressing mode used in instruction MOV M, C?

a) Direct

b) Indirect

c) Indexed

d) Immediate



37. In 8085 the direction of address business is

a)bidirectional

b)unidirectional out of MP

c)unidirectional int MP

d)none of the above



38. In 8085 the hardware interrupts are

a)TRAP,RST 6.5,RST 7.5, RST 5.5 and INTR

b)RST o, RST 1…..RST 7

c)both a b

d)none of the above



39. In the TRAP, RST 7.5, RST 6.5, RST 5.5, which is having top priority

a)TRAP

b)RST 7.5

c)RST 6.5

d)RST 5.5

40.In 8085 the no . of software interrupts are

a) 8

b)7

c)5

d)4



41. In the following interrupts which is the non-vectored interrupt

a)TRAP

b)INTR

c)RST 7.5

d)RST 6.5



42. Vector address for the TRAP interrupt is

a)0024 H

b)003C H

c)0034 H

d)002C H



43. In the following interrupt which is non-maskable interrupt

(a) Rst7.5

b) Rst 6.5

c) TRAP

d) INTR



44. Vector location Address for RST O Instruction is inflex

(a) ooooH

b) ooo8H

c) oo1oH

d)oo18H



45. In 8085 the Interput Acknowledge is represended by _______

(a) INTA

b)INTA

c) INTR

d) none of the above



46. The maximum number of I\o devices can be interfaced with 8085 in the I\o mapped I\o technique are

a) 128

b) 256

c) 64

d) 1024



47. The maximum number of I\o devices which can be interfaced in the memory mapped I\o technique are

a) 256

b) 128

c) 65536

d) 32768



48. Shadow Address will exist in

a) absolute decoding

b) linear decoding

c) partical decoding

d) none of the above



49. The Instructions used for data transfer in I\o mapped I\O are

a) IN, OUT

b) IN, LDA add

c) STA add

d) None of the above



50. Number of Address lines required to interface 1KB of memory are

a) 10

b)11

c) 12

d) 13






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